1. Field of the Invention
This invention relates to semiconductor memories and particularly to EEPROM cells and their manufacture.
2. Description of Related Art
FIG. 2 shows a conventional prior art EEPROM cell 10 with a P-substrate 11 covered in different regions with gate oxide layer 9 (150 .ANG..about.300 .ANG. thick) and tunnel oxide (TOX) layer 12 (80 .ANG..about.100 .ANG. thick). On the left side of the device is a select transistor ST including gate G above gate oxide layer 9 and select transistor N+ S/D regions 14, 14' formed in P- substrate 11. The select transistor ST usually needs to handle (pass) higher voltages to provide program or erase operations. Therefore, the gate oxide layer 9 for the select transistor ST is usually thicker. The N+ S/D regions 14, 14' are aligned with the periphery of gate G. Adjacent to the select transistor ST, on the right formed above the tunnel oxide (TOX) layer 12 is a stack of layers comprising floating gate FG formed on the tunnel oxide layer, interpolysilicon dielectric layer 16 overlying the floating gate layer FG and the control gate CG which overlies the interpolysilicon dielectric layer 16. The lower left edge of floating gate FG overlies the right end of N+ region 14' in the substrate 11. The lower right edge of floating gate FG overlies the left end of N+ region 14" in substrate 11.
EEPROM Electrically Erasable Programmable Read Only Memory devices have included a triple electrode variety with a select gate on the bottom, a floating gate in the middle and a control gate on top. Ajika et al "A Novel Cell Structure for 4M Bit Full Feature EEPROM and Beyond", IEEE IEDM pp 295-298 [reprint pp. 11.1.1-11.1.4] (1991) shows an EEPROM cell with a complicated three level resist and resist etch back process used to create a narrow tunnel oxide region. Ajika et al describes a configuration with the first polysilicon layer used as the select gate. The tunnel N+ region is merged with the source region of the select gate transistor. The tunnel N+ region is self-aligned to form a small N+ region, which is very small resulting in cell size reduction. In addition, the stacking of the floating gate/control gate (polysilicon 2/polysilicon 3) layers layers over a select gate (polysilicon 1) layer is shown. The Ajika et al design permits reduction of cell size because of the configuration described there.
The second and third layers of polysilicon form the floating gate and the control gate, which are stacked on the select gate. An important problem with the design of Ajika et al is that the EEPROM cell is fabricated with a complicated three level resist and resist etch back process used to create a narrow tunnel oxide region.